Floorplanning by Annealing on a Hypercube Architecture

Simulated annealing algorithms for VLSI layout tasks produce solutions of high quality but are computationally expensive. This thesis examines some parallel approaches to accelerate simulated annealing using message-passing multiprocessors with a hypercube architecture. Floorplanning is chosen as a typical application of annealing in physical design. Different partitioning strategies which map this annealing algorithm onto a hypercube architecture are presented. The objective in the design of these partitioning strategies is to exploit maximum parallelism in the algorithm within the constraints of a messagepassing multiprocessor environment. Besides utilizing the limited parallelism inherent in individual move evaluations, we also exploit the tolerance of annealing to errors in the value of the system cost function as seen locally in each processor. To map these partitioning strategies onto hypercube architectures, optimized message patterns are developed. Two parallel algorithms based on these partitioning strategies have been implemented on a 16 node Intel hypercube. Practical speedups roughly between 4 and 8 have been obtained on 16 processors for different strategies. The performance and solution quality of these algorithms is presented and critically analyzed. With respect to solutions produced by the analogous serial annealing algorithm, it is shown experimentally that the introduction of uncertainty in the parallel algorithms does not compromise the solution quality,